1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device comprising a capacitance adjustment section for conducting adjustment of wiring capacitance in a simple and rational manner.
The present specification is based on Japanese Patent Application, Unpublished, No. Hei 11-133286 which has been submitted in Japan and the content of which is incorporated as one portion of the present specification.
2. Description of the Related Art
FIG. 6 shows a sample construction, by conventional techniques, of a DRAM (Dynamic Random Access Memory). Up to now in semiconductor devices such as DRAM, package miniaturization has progressed considerably, in order to ensure that even with the increases in chip surface area associated with increasing memory capacity, the packaging density is not lowered. FIG. 6 shows an example of a CSP (chip size package) of a recently employed package type in which miniaturization has progressed significantly. In the CSP shown, a substrate 100 of a polyimide and a semiconductor chip 101 are fixed together with the chip surface facing the substrate and then sealed with a resin 102. A plurality of solder balls 103 which function as external terminals are provided on the lower surface of the substrate 100, while a plurality of pads (not shown in the figure) which function as chip wiring terminals are formed on the surface of the semiconductor chip 101. Each solder ball 103 and each pad are then connected electrically via copper wiring (not shown in the figure) formed on the upper surface of the substrate, and conducting materials (not shown in the figure) which are imbedded in through holes which penetrate through the substrate.
FIG. 7 is a schematic diagram showing a circuit block of a semiconductor chip. The chip comprises four memory cell blocks 104, and peripheral circuits 105 disposed about the periphery thereof. A single line of a plurality of pads 106 is formed in the center of the chip. In the figure, the wiring connected to the pads 106 has been omitted.
FIG. 8 shows the aforementioned DRAM viewed from beneath (from the solder ball side). In this example DRAM, the solder balls 103 on the substrate 100 are disposed in three lines on each of the left and right hand sides, while the pads 106 on the semiconductor chip 101 are disposed in a centrally positioned single line. Consequently, the wiring 107 for connecting each of the solder balls 103 and each of the pads 106, cannot be wired in a straight line, and must be suitably managed so as to avoid short circuits with other wiring 107. Moreover in FIG. 8 only a portion of the wiring 107 for connecting the solder balls 103 and the pads 106 is shown, although the remaining portions are wired in a similar manner.
However, as is evident from FIG. 8, because the length of each section of wiring 107 differs, the wiring capacitance of each section of wiring 107 will also differ. That is, the wiring capacitance from the external terminal of the DRAM to the pad will vary between pins, and left as is, there is a danger that the signal timing during the operations for the reading and writing of data will vary between pins, resulting in an error. Consequently, in this type of semiconductor chip, a capacitance adjustment section is usually provided for matching the wiring capacitance of each section of wiring.
FIG. 9 is a diagram showing the construction of a capacitance adjustment section of the aforementioned DRAM. The capacitance adjustment section 108 is basically constructed according to gate capacitance. That is, a capacitance is formed from a diffusion layer 109 formed on the surface of the semiconductor substrate, and gate electrodes 110a, 110b, 110c, and 110d which oppose the diffusion layer 109 via a gate insulating film. Furthermore, the plurality (four in the example shown) of gate electrodes 110a, 110b, 110c, 110d are provided for adjusting the capacitance value to various values, and each gate electrode 110a, 110b, 110c, 110d is connected to a first aluminum wiring 112 via a through hole 111. Each of the first aluminum sections of wiring 112 are connected respectively to a second aluminum wiring 114 via a through hole 113. Each of the second aluminum sections of wiring 114 is then connected to an input signal line 116 connected to an input pad 115.
Moreover in the present specification, xe2x80x9cfirst aluminum wiringxe2x80x9d refers to the first layer side (the lower layer) of aluminum wiring of a double layer wiring construction, whereas xe2x80x9csecond aluminum wiringxe2x80x9d refers to the second layer side (the upper layer) of aluminum wiring.
The gate length of each of the aforementioned four gate electrodes 110a, 110b, 110c and 110d is different, and referenced against the shortest gate length, the other gate lengths are set to values twice, three times, and four times as long respectively. Correspondingly, the capacitance values when referenced against the capacitance of the shortest gate length are twice, three times, and four times as large respectively. That is, the capacitance values are set so that the sequence of values from the shortest gate length to the longest gate length are, for example, 10fF (femtoFarad), 20fF, 30fF, and 40fF respectively.
In a DRAM provided with this type of capacitance adjustment section 108, the matching of wiring capacitance is conducted by assembling the semiconductor chip into a packaged state, and following measurement and evaluation of the electrical characteristics of the package, using the evaluation results to determine the input signal wiring sections which require additional capacitance to match the largest observed wiring capacitance, and then using the capacitance adjustment section 108 to add the necessary capacitance. In the case where capacitance is actually to be added, the value of the capacitance being added is altered by making a design change to the mask pattern of the second aluminum wiring, and connecting a gate capacitance with one of the four aforementioned capacitance values to the input signal wiring. Consequently, in the case of the example described above, by suitable combinations of the four different gate capacitances, capacitance additions of between 10fF and 100fF in increments of 10fF are possible.
However, the following problems arise with the conventional DRAM wiring capacitance adjustment methods described above.
Conducting adjustments of the wiring capacitance by combining gate capacitances for which the capacitance values are fixed, means that adjustments can only be made for limited increments (10fF in the case of the above example) and up to a limited upper limit (100fF in the case of the above example), and so fine adjustments in the capacitance value are difficult to achieve. Provision of a plurality of gate capacitances incorporating smaller capacitance values can be seen as a way of alleviating this problem, but in such cases the increase in the number of gate capacitances increases the surface area occupied by the capacitance adjustment section, resulting in an undesirable increase in the surface area of the chip. Furthermore, addition of each new gate capacitance requires a design change in the mask pattern of the lower layer, meaning the time and effort required for mask design changes increases undesirably.
An object of the present invention is to provide a semiconductor device comprising a capacitance adjustment section which enables the free setting of the amount of adjustment of a wiring capacitance and for which the adjustment operation can be carried out simply.
In order to achieve the above object, a semiconductor device of the present invention comprises the following two methods.
First, a first semiconductor device according to the present invention comprises a capacitance adjustment section for adjusting wiring capacitance, and the capacitance adjustment section further comprises a capacitance adjustment wiring which is connected to a target wiring for capacitance adjustment for adjusting wiring capacitance, and a constant voltage wiring which is formed on the same layer as the capacitance adjustment wiring and to which is applied a constant voltage. The capacitance adjustment wiring and the constant voltage wiring are positioned proximately and form a predetermined line capacitance, and this line capacitance is used to adjust a wiring capacitance of the target wiring for capacitance adjustment. The constant voltage wiring may utilize power supply voltage wiring or earthed voltage wiring, for example. Furthermore, the shape of the capacitance adjustment wiring and the constant voltage wiring may incorporate bent sections, or be formed in a shape resembling the teeth of a comb.
Compared with the conventional technology where a capacitance adjustment section utilizes gate capacitance, a capacitance adjustment section of a first semiconductor device according to the present invention uses a proximately positioned capacitance adjustment wiring and a constant voltage wiring to generate a line capacitance. Furthermore, the capacitance adjustment wiring and the constant voltage wiring is not simply disposed in straight lines, but rather incorporates bends and shapes resembling the teeth of a comb so that the two lengths of wiring intermesh. Consequently, if the facing surface area of the two lengths of wiring is increased, then a predetermined capacitance value can be achieved within a limited occupation area. Furthermore, the size of the added capacitance can be adjusted freely by increasing or decreasing the facing surface area of the two lengths of wiring.
As a result, the present invention enables the provision of a highly reliable semiconductor device in which errors resulting from signal timing deviations between pins during the operations of reading and writing data will not occur.
The capacitance adjustment section should preferably be formed from wiring provided in the uppermost layer of a multilayer interconnection structure. Such a construction enables the capacitance value to be adjusted by changing only the mask pattern of the uppermost wiring layer, with no modification of mask patterns of any of the lower layers being required. Consequently, the amount of time and effort required for mask design changes associated with adjustment of the wiring capacitance can be reduced.
In addition, in the case where the capacitance adjustment section is formed from wiring in the uppermost layer, the capacitance adjustment section can be layered on top of any elements or wiring constructed in layers other than the uppermost layer. Such a construction means separate space is not required for the capacitance adjustment section, and so the surface area occupied by the capacitance adjustment section can be reduced, contributing to a reduction in the surface area of the chip.
The wiring which is the object of the wiring capacitance adjustment process, termed the xe2x80x9ctarget wiring for capacitance adjustmentxe2x80x9d in the case of the present invention, may be an input signal line, or a clock signal line within a circuit.
A second semiconductor device according to the present invention also comprises a capacitance adjustment section for adjusting wiring capacitance, and the capacitance adjustment section further comprises an input pad formed from two conductive layers separated by an insulation layer. The two conductive layers form an interlayer capacitance, and this interlayer capacitance is used to adjust the wiring capacitance of input signal wiring. One specific method using this capacitance adjustment section for carrying out capacitance adjustment, comprises dividing at least one of the conductive layers which make up the capacitance adjustment section into a plurality of regions, and then adjusting the interlayer capacitance by either short circuiting or not short circuiting the two conductive layers for each of the plurality of divided regions.
Hence the capacitance adjustment section of the second semiconductor device according to the present invention generates an interlayer capacitance using the two conductive layers which form the input pads. Typically, the surface area of an input pad, and the thickness of an interlayer insulation layer are predetermined values, and so the value of the interlayer capacitance generated by the two conductive layers will also be a constant. Therefore the conductive layers which form an input pad are divided into a plurality of regions, and then for each of the plurality of divided regions, either a contact is formed between the two conductive layers to create a short circuit between the two layers so that that particular divided region will not generate a capacitance, or alternatively contact between the two layers is prevented so that no short circuit exists thereby ensuring that that particular divided region will form an interlayer capacitance. Consequently, by either increasing or decreasing the number of divided regions of the two conductive layers which are short circuited, the overall value of the interlayer capacitance for the input pad can be freely adjusted.
This method utilizes the input pads, which occupy a considerable surface area, as a capacitance adjustment section, and because additional space is not required for providing a capacitance adjustment section, this method is extremely effective, particularly in terms of reducing the surface area occupied by the capacitance adjustment section. In addition, the method also offers the advantage of enabling large capacitance adjustments. Furthermore, by dividing the conductive layer into small regions, small incremental capacitance adjustments are possible.
Moreover if possible, a conventional capacitance adjustment section utilizing gate capacitance may be replaced entirely with a capacitance adjustment section of the aforementioned first or second semiconductor devices according to the present invention, although the present invention is not limited to this situation, and appropriate combinations of conventional capacitance adjustment sections and capacitance adjustment sections of the first or second semiconductor devices according to the present invention are also possible. For example, following the generation of a certain capacitance using a conventional capacitance adjustment section, a capacitance adjustment section of the present invention could then be used for conducting fine adjustments to the wiring capacitance. So doing would enable both capacitance adjustment sections to work in cooperation in adjusting a wiring capacitance.